Why timeline binds
The binding constraint is timeline. Its gap metric is 50 % ◌ derived; the runner-up is hardware at 48.3 % ◌ derived, a margin of 1.7 % ◌ derived.
Regime R3 ◌ derived: a material supply shortfall; unmet demand is present and the binding constraint actively limits revenue.
Timeline binds at 50 % ◌ derived. The deployment schedule runs 24 months ◌ derived, with the utility queue at 24 months ◌ derived inside it. Revenue starts when the last gate clears; every month of schedule is a month of carry.
Sweat the current fleetRefresh each cycleRefresh blocked
Counterfactual, sweat versus refresh: at 132 kW ◌ derived design density no next chip generation is supportable — the nearest higher generation enters at 180 kW ◌ derived per rack. The refresh path holds the current generation and matches the sweat path over the analysis horizon; the facility supports 2 ◌ derived generation classes over 10 years ◌ derived.
Whether that is acceptable is a judgment this model does not make.