Why timeline binds
The binding constraint is timeline. Its gap metric is 75 % ◌ derived; the runner-up is capital at 72.9 % ◌ derived, a margin of 2.1 % ◌ derived.
Regime R4 ◌ derived: a severe structural imbalance; supply cannot meet demand at maximum utilisation and several constraints sit near their bounds.
Timeline binds at 75 % ◌ derived. The deployment schedule runs 36 months ◌ derived, with the utility queue at 36 months ◌ derived inside it. Revenue starts when the last gate clears; every month of schedule is a month of carry.
Sweat the current fleetRefresh each cycleRefresh blocked
Counterfactual, sweat versus refresh: at 80 kW ◌ derived design density no next chip generation is supportable — the nearest higher generation enters at 120 kW ◌ derived per rack. The refresh path holds the current generation and matches the sweat path over the analysis horizon; the facility supports 1 ◌ derived generation classes over 5 years ◌ derived.
Whether that is acceptable is a judgment this model does not make.